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200mA & 250mA SmartLDOsTM
POWER MANAGEMENT Description
The SC1531(A) is designed to maintain a glitch-free 3.3V output when at least one of two inputs, 5V (VIN) and 3.3V (VAUX), is present.
SC1531(A)
Features
Glitch-free transition between input sources Internal logic selects input source Gate drive for external PMOS bypass switch 5V detection with hysteresis 1% regulated output voltage accuracy 200mA load current capability (250mA for SC1531A) Remote sense SO-8 package
u u u u Whenever VIN exceeds a predetermined threshold value, u the internal 3.3V linear regulator is enabled, and DR is u pulled high. u When VIN falls below a lower threshold value, DR is pulled u
low and the internal linear regulator is turned off. DR has been designed to drive the gate of an external low threshold P-channel MOSFET, which can be used to connect the 3.3V supply directly to the regulator output. This ensures an uninterrupted 3.3V output even if VIN falls out of specification. A typical RDS(ON) of 400mW is recommended (320mW for SC1531A). When both supplies are simultaneously available, the drive pin (DR) will be pulled High, turning off the external PMOS switch. The internal 5V detector has its upper threshold (for VIN rising) set to 4.18V (typical) while the lower threshold (for VIN falling) is at 4.05V (typical) giving a hysteresis of approximately 130mV. The SENSE pin, which is connected to the load, connects internally to the inverting input of the LDO error amplifier. It enables tight regulation of the load voltage (while the 5V supply is present) despite variations in load current. The SC1531(A) is available in the popular SO-8 surface mount package.
Applications
u u u u u
Desktop Computers Network Interface Cards (NICs) PCMCIA/PCI Interface Cards CardbusTM Technology Power supplies with multiple input sources
Typical Application Circuit
Notes for Typical Application Circuit: (1) External switch (Q1): use Motorola MGSF1P02ELT1 or equivalent (PMOS, typical Gate Threshold Voltage = 1V, typical RDS(ON) = 0.4W at VGS = 2.5V) for SC1531. Use Vishay Si2301DS or equivalent for SC1531A. (2) Connection of VAUX (pin 3) is optional.
Q1
U1 5V 3.3V 1 2 3 4 C1 0.1uF C2 4.7uF C3 0.1uF VIN DR NC VO VAUX SENSE GND NC SC1531 8 7 6 5 C4 4.7uF C5 0.1uF 3.3V OUT
Revision 1, December 2000
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SC1531(A)
POWER MANAGEMENT Absolute Maximum Rating
Parameter Input Supply Voltage Auxi li ary Supply Voltage LD O Output C urrent (SC 1531) LD O Output C urrent (SC 1531A) Thermal Impedance Juncti on to Ambi ent Thermal Impedance Juncti on to C ase Operati ng Ambi ent TemperatureRange Operati ng Juncti on Temperature Range Storage Temperature Range Lead Temperature (Solderi ng) 10 Sec. ESD Rati ng Sy mbol VIN VAUX IO IO q JA q JC TA TJ TSTG TLEAD V ESD Maximum -0.5 to +7 -0.5 to +7 200 250 130 47 -5 to +70 -5 to +125 -65 to +150 300 2 U nits V V mA mA C /W C /W C C C C kV
Electrical Characteristics
Unless specified: TA = 25C, VIN = 5V, VAUX = 3.3V, IO = max. rated, CO = 4.7F. Values in bold apply over full operating temperature range.
Parameter VIN Supply Voltage Qui escent C urrent
Sy mbol
Test C onditions
Min
Ty p
Max
U nits
VIN IQ
VAUX = 0V VIN = 5V, VAUX = 0V, IO = 0mA
4.3
5.0 7.0
5.5 10.0 11.0
V mA
VIN = 5V, VAUX = 3.3V, IO = 0mA
7.5
10.0 12.0
mA
Reverse Leakage From VAUX
IVIN
VAUX = 3.6V, VIN = 0V, IO = 0mA
1.0
10 20
A
VAU X Supply Voltage Qui escent C urrent VAUX IQ(AUX) VAUX = 3.3V, VIN = 0V, IO = 0mA 3.0 3.3 0.8 3.6 1.5 2.0 VAUX = 3.3V, VIN = 5V, IO = 0mA 0.6 1.0 2.0 Reverse Leakage From VIN IVAUX VIN = 5.5V, VAUX = 0V, IO = 0mA 7 50 100
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V mA
mA
A
SC1531(A)
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: TA = 25C, VIN = 5V, VAUX = 3.3V, IO = max. rated, CO = 4.7F. Values in bold apply over full operating temperature range.
Parameter 5V D etect(1)(2)(3) Low Threshold Voltage Hysteresi s
Sy mbol
Test C onditions
Min
Ty p
Max
U nits
VTH(LO) VHYST
VIN Falli ng
3.90 90 80
4.05 200
4.20
V mV
Hi gh Threshold Voltage VO LD O Output Voltage
VTH(HI)
VIN Ri si ng
4.30
V
VO
IO = 20mA 4.3V VIN 5.5V, 0mA IO IO(MAX) 3.9V VIN 4.3V, VAUX = 3.3V, 0mA IO IO(MAX)(4)
3.267 3.234 3.000
3.300
3.333 3.366
V
Li ne Regulati on
REG(LINE)
VIN = 4.3V to 5.5V
0.12
0.40 0.60
%
Load Regulati on
REG(LOAD)
IO = 20mA to IO(MAX)
0.12
0.40 0.60
%
SEN SE SENSE Pi n Impedance DR D ri ve Voltage V DR 4.3V VIN 5.5V, IDR = 200A 3.4 3.3 VIN < VTH(LO), IDR = -200A 35 150 200 Peak D ri ve C urrent IDR(PK) Si nki ng: VIN = 3.9V, VDR = 1V; Sourci ng: VIN = 4.3V, (VIN - VDR) = 2V D ri ve Hi gh D elay(1)(5) tDH C DR = 1.2nF, VIN rampi ng up, measured from VIN = VTH(HI) to VDR = 2V D ri ve Low D elay(1)(5) tDL C DR = 1.2nF, VIN rampi ng down, measured from VIN = VTH(LO) to VDR = 2V 0.5 7 6 0.5 1.0 2.0 1.0 2.0 s s mA mV VIN - 0.8 V RSENSE 6.0 8.5 kW
See next page for Notes.
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SC1531(A)
POWER MANAGEMENT Electrical Characteristics (Cont.)
Notes: (1) Guaranteed by design. (2) See 5V Detect Thresholds below. (3) Recommended source impedance for 5V supply: 0.25W (0.2W for SC1531A). This will ensure that IO x RSOURCE < VHYST, thus avoiding DR toggling during 5V detect threshold transitions. (4) In Application Circuit on page 1. (5) See Timing Diagram below.
5V Detect Thresholds(1)
Note: (1) VIN rise and fall times (10% to 90%) to be
100s.
Timing Diagram(1)
Note: (1) VIN rise and fall times (10% to 90%) to be 100ns.
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SC1531(A)
POWER MANAGEMENT Pin Configuration
(TOP VIEW)
Ordering Information
Part N umber(1) SC 1531C S.TR SC 1531AC S.TR Output C urrent 200mA 250mA P ackag e SO-8 SO-8
Note: (1) Only available in tape and reel packaging. A reel contains 2500 devices.
(SOIC-8)
Block Diagram
Pin Descriptions
Pin 1 2 3 4 5 6 7 8 Pin N ame VIN NC VAUX GND NC SENSE VO DR Pin Function Thi s i s the mai n i nput supply for the IC , nomi nally 5V. No connecti on. Thi s i s the auxi li ary i nput supply, nomi nally 3.3V. C onnecti on of thi s pi n i s opti onal, and wi ll sli ghtly i mprove the turn-on ti me of the external MOSFET. Leave floati ng i f not used. Logi c and power ground. No connecti on. Sense pi n for VO. C onnect to VO at the load to mi ni mi ze voltage drop across PC B traces. If remote sense functi on i s not requi red, connect di rectly to pi n 7. LD O 3.3V output. D ri ver output for external P-channel MOSFET pass element.
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SC1531(A)
POWER MANAGEMENT Typical Characteristics
Quiescent Current vs. Main Input Voltage vs. Junction Temperature, VAUX = 0V
8 7 6 5 IQ (mA) 4 3 2 1 0 0 1 2 3 VIN (V) 4 5 6 -5C 25C 125C IQ (mA) IO = 0mA VAUX = 0V 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 VIN (V) 4 5 6 -5C 25C 125C IO = 0mA VAUX = 3.3V
Quiescent Current vs. Main Input Voltage vs. Junction Temperature, VAUX = 3.3V
Auxiliary Quiescent Current vs. Auxiliary Input Voltage vs. Junction Temperature, VIN = 0V
0.6 IO = 0mA VIN = 0V 0.5
Auxiliary Quiescent Current vs. Auxiliary Input Voltage vs. Junction Temperature, VIN = 5V
0.7 0.6 0.5 IO = 0mA VIN = 5V
0.4 IQ(AUX) (mA)
IQ(AUX) mA
0.4 0.3 0.2
0.3
0.2 -5C 25C 125C 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 VAUX (V) 2.4 2.7 3 3.3 3.6
0.1
0.1 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 VAUX (V) 2.4 2.7 3
-5C 25C 125C 3.3 3.6
0
LDO Output Voltage vs. Junction Temperature
3.34 3.33 3.32 3.31 VO (V) 3.30 3.29 3.28 3.27 3.26 -25 0 25 50 TJ (C) 75 100 125 IO = 200mA VIN = 5V
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SC1531(A)
POWER MANAGEMENT Typical Characteristics (Cont.)(1)
Drive High Delay Drive Low Delay
Trace 1: VIN stepping from 3V to 5.5V Trace 2: DR going high at VTH(HI) tDH < 225ns
Trace 1: VIN stepping from 5.5V to 3V Trace 2: DR going low at VTH(LO) tDL < 125ns
VO(MIN) With VIN Rising(2)
VO(MIN) With VIN Falling(2)
Trace 1: VIN with 3A charging a 1500uF capacitor Trace 2: DR going high at VTH(HI) Trace 3: VO, offset 3.3V. VO(MIN) = 3.19V
Trace 1: VIN - discharging a 1500uF capacitor Trace 2: DR going low at VTH(LO) Trace 3: VO, offset 3.3V. VO(MIN) = 3.14V
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SC1531(A)
POWER MANAGEMENT Typical Characteristics (Cont.)(1)
Load Transient Response Load Transient Response
Trace 1: VO Trace 2: IO stepping from 0mA to 200mA Notes: (1) In Application Circuit on page 1. (2) IO = 200mA.
Trace 1: VO Trace 2: IO stepping from 200mA to 0mA
Applications Information
Introduction The SC1531(A) is intended for applications such as power managed PCI and network interface cards (NICs), where operation from a 3.3V VAUX supply may be required when the 5V supply has been shut down. It provides a very simple, low cost solution that uses very little pcb real estate. During regular operation, 3.3V power for the PCI card is provided by the SC1531(A)s on-board low dropout regulator, generated from the 5V supply. When the 5V supply is removed and 3.3V VAUX is available, the SC1531(A) connects this supply directly to its output using a tiny SOT-23 external p-channel FET. Connection of pin 3 (VAUX) to the 3.3V supply is optional, and adds active pull-down to the Drive pin. Component Selection Output capacitors - Semtech recommends a minimum bulk capacitance of 4.7F at the output, along with a 0.1F ceramic decoupling capacitor. Increasing the bulk capacitance will improve the overall transient response. The device is very tolerant of capacitor value and ESR variations, in fact, any combination of capacitors with C 4.7F and ESR < 1W is sufficient for stability. This
a 2000 Semtech Corp. 8
target is easily met using surface mount ceramic or tantalum capacitors. Input capacitors (5V) - Semtech recommends the use of a 4.7F ceramic or tantalum capacitor plus a 0.1F ceramic capacitor at the input. This allows for the device being some distance from any bulk capacitance on the rail. Additionally, input droop due to load transients is reduced, improving load transient response. Input capacitors (3.3V) - Semtech recommends decoupling this pin (if used) with a 0.1F ceramic capacitor. P-channel bypass FET - selection of the external FET is determined by two main requirements: 1) the FET has to have a very low gate threshold (typically ~1V) in order to be sufficiently turned on with VGS 3.3V. 2) the FET RDS(ON) must be low enough such that:
VAUX - (I O ( MAX ) * R DS ( ON ) ) VO ( MIN )
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SC1531(A)
POWER MANAGEMENT Applications Information (Cont.)
(Remember that at 125C, RDS(ON) is generally 1.5x the value at 25C.) Thermal Considerations When operating from the 5V supply, the power dissipation in the SC1531(A) is approximately equal to the product of the output current and the input to output voltage differential:
PD (VIN - V OUT ) * I OUT
This is readily achievable using pcb copper area to aid in conducting the heat away from the device (see Figure 1 on page 10). Heatsinking the bypass FET is not necessary - its power dissipation is given by:
PD ( MAX ) = (I O ( MAX ) ) 2 * R DS ( ON )( MAX )
For IO = 200mA, and RDS(ON) = 0.6W, PD = 24mW. Layout Considerations While layout for linear devices is generally not as critical as for a switching application, careful attention to detail will ensure reliable operation. See Figure 1 on page 10 for a sample layout. 1) Attaching the part to a larger copper footprint will enable better heat transfer from the device, especially on PCBs where there are internal ground and power planes. 2) Place the bulk and decoupling capacitors close to the device for optimal transient response. 3) If the SENSE lead is being used, route it to the load using a seperate trace from the main VO path. If it is not being used, connect to pin 7 as shown. 4) The external bypass FET is shown close to the device for convenience only. Since it is not being switched, longer gate drive traces can be used without problem.
The absolute worst-case dissipation is given by:
PD ( MAX ) = (VIN
( MAX )
- VO
( MIN )
)* I
O ( MAX )
+ VAUX
( MAX )
* I Q ( AUX )( MAX )
Note that the VAUX (MAX) x I Q(AUX) term does not apply if VAUX is not available or not connected. Inserting VIN = 5.5V, VO = 3.234V, IO = 200mA, VAUX = 3.6V and IQ(AUX) = 2mA yields:
PD ( MAX ) = 0 . 46 W
Using this figure, we can calculate the maximum thermal impedance allowable to maintain TJ 125C:
R TH ( J - A )( MAX ) =
(T
J( MAX )
- TA (MAX ) )
PD( MAX )
=
(125 - 70 ) = 120 C / W
0 .46
R TH ( J - C )( MAX ) = 47 C / W , therefore R TH ( C - A )( MAX ) = 73 C / W
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SC1531(A)
POWER MANAGEMENT Application Information (Cont.)
Top Copper
Top Silk Screen
Figure 1: Suggested pcb layout based upon Application Circuit on Page 1.
Bill of Materials (Application Circuit Page 1)
Qty. R eference 3 2 1 1 C 1, C 3, C 5 C 2, C 4 Q1 U1 P art/D escription 0.1F cerami c 4.7F cerami c or tantalum MGS F1P 02E LT1 S i 2301D S S C 1531(A )C S Vendor Vari ous Vari ous Motorola V i shay S emtech P -channel, low gate threshold, 400mW (S C 1531) P -channel, low gate threshold, 200mW (S C 1531A ) N otes C 1 not requi red i f VA UX not connected
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SC1531(A)
POWER MANAGEMENT Outline Drawing - SO-8
JEDEC REF: MS-012AA
Land Pattern - SO-8
Contact Information
Semtech Corporation Power Management Products Division 652 Mitchell Rd., Newbury Park, CA 91320 Phone: (805)498-2111 FAX (805)498-3804
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